Pipeline: 1 A particular (fictional) CPU has the following internal units and timings (WR and RR are write/read registers, ALU does all logic and integer operations and there is a separate floating point unit. There are 5 basic instruction types: 1. LOAD ID+RR+ALU+MEM+WR : 660ps 2. STORE: ID+RR+ALU+MEM: 600ps 3. LOGIC/INTEGER: ID+RR+ALU+RW: 460ps 4. FLOATING POINT: ID+RR+FPU+RW: 560ps 5. BRANCH: ID+RR+ALU: 400ps 1 cycle is 660ps for this machine, on the assumption that all instructions take 1 cycle (ignore memory delays): Design a pipelin. Give number of stages operations in each stage new clock rate pipeline. speedup compared to original 600ns instruction rate with no Would this pipeline be able to take advantage of data forwarding? If yes, which stages would be involved?

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